Developments in modern electronic devices have resulted in smaller and smaller circuits and devices in general. As devices become smaller and smaller, particularly with respect to circuit-level components, the leakage current of a given circuit or design has become increasingly important to manage. Moreover, as technology and advancements result in smaller-scale devices, the leakage current, typically an undesirable stray current that flows through an electronic device, which is ordinarily small relative to the operating current and/or voltages of a device, approaches a higher percentage of the total operating currents of the device. Accordingly, as technology drives toward smaller circuits, efforts have also been undertaken to reduce the leakage current to a negligible or otherwise, manageable level. Additionally, developments in device performance have encouraged investigation of various methods and techniques to reduce the power required to operate a device.
For example, clock gating is a common-technique for reducing the power of circuits, or even entire units, during clock cycles in which the circuits or components are not in use. When the clock of a register, for example, is gated or otherwise turned off, the register and its output maintain the previous state. Thus, a switching power in the circuit can be reduced. However, reduction in switching power does not necessarily impact the leakage current of the circuit to a substantial enough degree to reduce problems associated with a relatively high leakage current.
An example of a circuit that has undesirable leakage current is FIG. 1 of the drawings. The reference numeral 100 generally designates conventional logic design that comprises combinational logic 104, register inputs 102, and register outputs 106. With the logic 100, data is input into the combinational logic 104 through the register inputs 102, and resulting data is output from the combinational logic 104 to the register outputs 106. However, the combinational logic 104 utilizes thin film transistors, such as Positive channel Metal Oxide on Silicon (PMOS) transistors; thus, there can be an undesirable leakage current.
Manipulating or otherwise controlling the input data into the register inputs 102 of a circuit 100 can be a useful technique to help reduce a leakage current when the circuits are not actively in use, particularly in very large scale integration (VLSI) circuits. Several techniques have been developed in an effort to maximize the use of an appropriately configured minimum leakage vector. For example, one common technique includes adding multiplexer logic, as depicted below in conjunction with FIG. 3, between the input registers (not shown) and the target combinational logic circuit 104. In particular, the input multiplexer method adds a multiplexer for each output of an input register (not shown), thereby allowing a selection between data, passed to the combinational logic circuit 104 in ordinary operation, and a minimum leakage vector, applied to the combinatorial circuit as required, through an appropriate selection of the multiplexer. However, this method often incurs timing delays to the circuits which might not be acceptable for high-performance designs because the cycle time of system can be increased.
Other techniques employ scan-chain circuitry typically included in many electronic devices in order to facilitate testing and other diagnostic operations. For example, in many systems, latch bits are often linked together to form a scan chain. In particular, many scan-based methods are configured to switch the entire system or scan chain into a scan mode, and apply a minimum leakage vector as a scan entry. However, switching to a scan mode in some systems can require waiting several clock cycles, during which time previously issued commands in a pipeline are completed and cleared.
Referring to FIG. 2 of the drawings, the reference numeral 200 generally designates an n-bit scan register. The register 200 comprises a local clock buffer (LCB) 202 and latch bits 250, 252, and 254. Each latch bit 250, 252, and 254 further comprises one multiplexer (mux) 204, 206, and 208, and one latch 210, 212, and 214. Typically, the register 200 is utilized for n-bits, so that a latch bit, such as the latch bits 250, 252, and 254, is utilized for each bit. FIG. 2, however, only depicts latch bits for the purposes of illustration, but there could be any number of latch bits as desired.
The register 200 is initiated by a clocking signal. The clocking signal is received at the LCB 202 through the communication channel 234. However, for the LCB 202 to generate a local clock signal, which is communicated to each latch 210, 212, and 214 through the communication channel 229, the LCB 202 also should receive an activation signal and a select signal (SL) through the communication channels 236 and 232, respectively. The SL signal indicates the mode of operation of the register 200, where a ‘1’ indicates scan mode and a ‘0’ indicates normal mode.
Depending on the mode of operation, the register 200 operates as normally latching data or as scanning data for testing purposes. In addition to providing the SL signal to the LCB 202, the SL signal is provided to each mux 204, 206, and 208 through the communication channel 232. In normal mode (SL=0), data is input into each muxes 204, 206, and 208 through the communication channels 218, 220, and 222, respectively. When properly clocked, the data can be latched into each of the latches 210, 212, and 214. Then, the latched data can be output from the latches 210, 212, and 214 through the communication channels 224, 226, and 230, respectively.
In scanning mode (SL=1), the operation of the register 200 is substantially different. Scan-in data is input into the mux 204 through the communication channel 216. The scan-in data is then latched in the latch 210, when enabled by the local clocking signal provided by the LCB 202. The latch 210 can then output the latched scan-in data through the communication channel 224, which is also input into the mux 206. The mux 206 can then latch the scan-in data in the latch 212, when clocked. The process then successively continues through the latch bits 250, 252, and 254 until the mux 208 receives the scan-in data. The mux 208 can then latch the scan-in data in the latch 214, where the latch 214 can output scan-out data through the communication channel 230.
The scan function (SL=1) can be used for applying the Low Leakage Vector (LLV) with small hardware overhead without having an adverse on the timing of combinational logic, such as the combinational logic 104, coupled to the register 200. When scanning in the LLV, the data is shifted through the latches 210, 212, and 214 one bit at a time. However, the chain can be very long, exceeding 1000 bits. Therefore, many cycles are required to scan in all of the data. Additionally, the power used for switching can outweigh the power saved due to the reduced leakage current once the LLV is applied.
When scanning, the process of scanning always updates the entire chain which usually consists of several registers, such as the register 200. Therefore, applying the LLV as result of a scan operation requires that all registers of that scan chain are updated. In cases where the entire system can be transitioned in a “low-leakage” state, the scan method can be useful. However, in other cases, such as cases for powering down infrequently used subunits while the remainder of the system is functioning, the scan method is not as effective.
Another solution is to utilize intermediate multiplexers. Referring to FIG. 3 of the drawings, the reference numeral 300 generally designates a multiplexed logic system. The system 300 comprises register inputs 302, a mux 308, and combinational logic 304. There can be a number of register inputs and muxes; however, for the purposes of illustration, only one mux and one register input are shown.
Essentially, intermediate muxes, such as the mux 308, are interposed between the register inputs 302 and the combinational logic 304. The mux 308 then can control the function of the system 300. Based on the select signal input through the communication channel 310 to the mux 308, allow for selection between normal mode (select=0) and low-leakage mode (select=1). In normal mode (select=0), data is passed through the mux 308 from the register inputs 302 to the combinational logic 304. However, in low-leakage mode 2(select=1), LLV data is input into mux 308 through the communication channel 312, which is then passed onto the combinational logic 304.
In the system 300, LLV is constant, allowing the muxes, such as the mux 308, to be simplified to other logical structures, such as AND gate or OR gates. However, logic is clearly added to the input paths of the combinational logic 304. The additional logic, therefore, adds delay to the timing critical paths of the combinational logic 304.
Therefore, there is a need for a system and/or method for reducing leakage currents that addresses at least some of the problems and disadvantages associated with conventional systems and methods.